1. Field of the Invention
The present invention relates to an integrated circuit of a semiconductor memory and more particularly to a synchronous pipeline semiconductor memory for high-speed operations.
2. Description of Related Art
As electronic systems in computer, communication, and other applications increase in capacity and operating speed, the semiconductor memories used therein must also increase in capacity and speed to meet the needs of the system. High-speed static random access memories (SRAMs), for instance, are an important cache memory for computers and communication applications. Because data processors operate at extremely high speeds, faster operating cache memories are desirable to provide improved system performance. Double data rate and pipelined burst methods have been disclosed as ways of increasing operating speeds to meet system demands.
FIGS. 1 and 2 are a block diagram and related timing flowchart, respectively, of a prior art synchronous semiconductor memory. The prior art system shown in FIGS. 1 and 2 is disclosed by Leach, et al, in U.S. Pat. No. 5,923,615 (Leach), issued Jul. 13, 1999. In Leach, a synchronous pipeline burst memory operates at a rapid clock speed without additional pipeline stages. The memory is constructed having an address input buffer 22, an address register 24, a synchronous control circuit 26, a data register 28, a data output buffer 30, and an asynchronous memory core 40. The address register 24 latches burst addresses during the first cycle, and the latched burst address is sent to an input of the asynchronous memory core 40, which includes a plurality of memory cells.
The output data sent out of the asynchronous memory core 40 is not latched until the third cycle. The third cycle is generated after the second cycle of a periodic clock signal, which in turn follows the first cycle. As a result, the burst operation cycles of Leach better guarantee sensing operations according to a typical pipeline rule by securing a longer time between the activation of word lines and the distinction of bit lines. Unfortunately, however, Leach fails to reduce the cycle time of the memory because the data output from a memory cell at the activation time of a latch signal from the synchronous control circuit 26 is not latched until the third cycle of the periodic clock signal. The cycle time of the Leach memory is therefore determined by the time taken from initiating an external clock signal to the latching of data at the data register. Errors in data latching and unstable sensing operations may occur if the operational cycle time is shorter than a pre-set time.
In the synchronous pipeline memory field, research is continuously being conducted on ways to obtain a shorter cycle time. Although conventional pipeline operations, such as those illustrated in FIG. 3, are well known in this field, they will be described generally in this application to provide a more thorough understanding of the various aspects and embodiments of the present invention.
FIG. 3 illustrates general read operation timing of a two-stage synchronous pipeline memory. Referring to FIG. 3, if an external address XADD is input during the first cycle T1 of an external clock signal XCLK, the address is decoded to the row and column selecting signals SWL, Yi, respectively, during the first cycle. The row and column selecting signals SWL, Yi are then transmitted to the memory cell array. The row and column selecting signals SWL, Yi operate to select a corresponding memory cell, such that the charge of the selected memory cell will be shared with corresponding shared data lines SDL, /SDL.
After the charge is shared with the data lines SDL, /SDL, a block sense amplifier BSA (or the first sense amplifier) begins its operations in response to the inputting of a sense amplifier enable signal PSAL. The block sense amplifier senses and amplifies a difference in the levels of voltage developed among the data lines SDL, /SDL and provides this amplified signal as cell data (or storage information) of the selected memory cell to the main data lines MDL, /MDL. More specifically, the cell data is latched through an output buffer, commonly connected to the main data lines MDL, /MDL, to a data register connected to the rear end of an output buffer.
The data register shifts the latched cell data to an output driver in response to the second clock signal, sent during the second cycle of the external clock signal XCLK. The cell data is driven by the output driver and then output to an external data input/output terminal I/O. In this circuit, the cycle time is determined as the time from the shift of an external clock signal to the latch of data to the data register. The clock to data speed is determined as the time from activation of the second clock signal Kdata to the external output of cell data latched at the data register through an output driver.
Therefore, this two-stage synchronous pipeline memory is limited in its ability to reduce the cycle time because it takes a long time for cell data to become latched to the data register. Accordingly, a need remains for an alternative memory structure and method that is capable of reducing the cycle time by shortening the time between the shifting of an external clock signal and the latching of data to the data register.
It is an object of the present invention to provide a semiconductor memory that has a reduced cycle time and a faster operating cycle.
It is another object of the present invention to provide a method for operating a semiconductor memory with a reduced cycle time.
It is a still another object of the present invention to provide a high speed synchronous semiconductor memory having a structure that reduces the time to latch data to a data register after the transmission of an external clock signal.
It is yet another object of the present invention to provide a method of operating a high-speed synchronous semiconductor memory with a reduced time for latching data to a data register following an external clock signal.
A semiconductor memory according to a preferred embodiment of this invention includes a three or more-stage pipeline. The semiconductor memory includes the basic structure of a two-stage pipeline and additionally includes a data register between a sense amplifier and a common data line.
A method for operating a semiconductor memory according to a preferred embodiment of the present invention proceeds by latching output data of a block sense amplifier to a first data register, connected with a front end of an output buffer, during the first clock cycle. The latched data is then latched to a second data register, connected with a rear end of the output buffer, during the second clock cycle. The data stored at the second data register is outputted externally through an output driver during the third clock cycle.